A top-exposed semiconductor package of the prior art is shown in FIG. 1, which includes a semiconductor chip 2′, which includes the source and gate electrodes on the top surface and a drain electrode on the bottom surface, flipped and mounted on a lead frame 1′, a copper plate 3′ attached on the drain electrode of the flipped chip 2′ and a molding layer covering the lead frame 1′ and the chip 2′ with the top surface of the copper plate 3′ exposed from the top surface of the molding layer. The top-exposed semiconductor package of FIG. 1 has dual-channel heat dissipation through the top surface of the copper plate 3′ and the bottom surface of the lead frame 1′.
However, the surface of chip 2′ is deposited with some solder balls to prevent the overflowing of the adhesive material used for mounting the chip 2′ on the lead, as well as providing some spaces 6′ in the lead frame 1′ for preventing short-circuit between the source and the drain or the gate and the drain of the chip 2′. As such, the product cost is increased, the process is complicated and the effective contact area of the source electrode of the chip 2′ is reduced. In addition, the space 6′ increases the size of the entire package.
It is within this context that embodiments of the present invention arise.